Conference Program

All the paper, poster and keynote presentations will be performed at the Classroom Rogers (additional information on how to reach it here).

The posters will be shown in Classroom Gamma, the suggested size and format is A0 portrait. We encourage the authors to keep their poster displayed during all the days of the conference. Authors can bring their poster during the early registration on July 9, 2018 or before the short paper session on July 10, 2018.

The bootcamp on Chiesel HDL on July 9, 2018 and the workshop on FPGA-based Accelerated Cloud Computing on July 13, 2018 will be held at Classroom Y.1.

July 9, 2018
09-00 - 18.00 Bootcamp on Chisel HDL @ Classroom Y.1
Main Speaker: David Donofrio​ ​- Lawrence Berkeley National Laboratory

09.00 - 13.00 Introduction and fundamentals on Chisel HDL
13.00 - 14.00 Lunch
14.00 - 18.00 Hands on session
16.00 - 18.00 Early registration to ASAP 2018 @ Classroom Rogers
July 10, 2018
08.30 - 09.00 Registration
09.00 - 10.00 Keynote: How to Make Sparse Fast
Saman P. Amarasinghe, Professor and Associate Department Head, MIT
Session chair: Emanuele Del Sozzo, Politecnico di Milano, Italy
10.00 - 10.30 Coffee break
10.30 - 12.15 Paper session - Applications: Image Processing
(4 full paper presentations)
Session chair: Zhiru Zhang, Cornell University, New York, USA
20 Julian Sarcher, Christian Scheglmann, Alexander Zöllner, Tim Dolereit, Michael Schäferling, Matthias Vahl and Gundolf Kiefer: A Configurable Framework for Hough-Transform-Based Embedded Object Recognition Systems
76 Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci and Marco Domenico Santambrogio: Five-point algorithm: an efficient cloud-based FPGA implementation
59 Qiong Chang and Tsutomu Maruyama: Real-time high-quality stereo matching system on GPU
14 Xiebing Wang, Christopher Kiwus, Canhao Wu, Biao Hu, Kai Huang and Alois Knoll: Implementing and Parallelizing Real-time Lane Detection on Heterogeneous Platforms
12.15 - 13.30 Lunch
13.30 - 14.30 Keynote: Deep reinforcement learning and algorithmic risks in finance
Marcello Paris - Head of Math & IT research, R&D Dept. UniCredit
Session chair: Marco Rabozzi, Politecnico di Milano, Italy
14.30 - 15.45 Paper session - Design Methods and Domain Specific Languages
(3 full paper presentations)
Session chair: Mario Porrmann, Bielefeld University, Germany
73 Francis Russell, James Targett and Wayne Luk: From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations
78 Emanuele Del Sozzo, Riyadh Baghdadi, Saman Amarasinghe and Marco Domenico Santambrogio: A Unified Backend for Targeting FPGAs from DSLs
23 Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner and Frank Hannig: Solving Maxwell’s Equations with Modern C++ and SYCL: A Case Study
15.45 - 16.15 Coffee break
16.15 - 18.15 Short paper session
(12 short paper presentations)
Session chair: Emanuele Del Sozzo, Politecnico di Milano, Italy
28 Antonio De Vita, Gian Domenico Licciardo, Danilo Pau, Luigi Di Benedetto, Emanuele Plebani and Angelo Bosco: Low-power Design of a Gravity Rotation Module for HAR Systems Based on Inertial Sensors
91 Linlong Xiao, Nanzhi Wang and Guocai Yang: A Reading Comprehension Style Question Answering Model Based On Attention Mechanism
13 Maxime France-Pillois, Jérôme Martin and Frédéric Rousseau: Linux synchronization barrier on MPSoC: hardware/software accurate study and optimization
68 Eric Flamand, Davide Rossi, Francesco Conti, Antonio Pullini, Igor Loi, Florent Rotenberg and Luca Benini: GAP-8: A RISC-V SoC for AI at the Edge of the IoT
21 Hesam Zolfaghari, Davide Rossi and Jari Nurmi: An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks
8 Daolu Zha, Xi Jin, Rui Shang and Pengfei Yang: A Real-Time Learning-Based Super-Resolution System Using Direct Dimple Functions
66 Zulun Zhu, Shaowu Yang and Huadong Dai: Vision-Assisted Loop Closure Detection and Correction for Laser-Based SLAM
88 Bin Zou and Yantao Li: Touch-based Smartphone Authentication Using Import Vector Domain Description
70 Daniel Klimeck, Hanno Gerd Meyer, Jens Hagemeyer, Mario Porrmann and Ulrich Rückert: Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications
24 Kaoru Saso and Yuko Hara-Azumi: Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices
63 Antoniette Mondigo, Kentaro Sano and Hiroyuki Takizawa: Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem
48 Mitali Sinha, Sri Harsha Gade, Wazir Singh and Sujay Deb: Data-flow Aware CNN Accelerator with Hybrid Wireless Interconnection
19.30 - 21.30 Cheese and wine welcome event
ASAP 2019 announcement
Politecnico di Milano - Classroom Rogers
July 11, 2018
09.00 - 10.00 Keynote: How open source designs will drive the next generation of HPC Systems
David Donofrio, Group Lead & Computer Systems Engineer at Lawrence Berkeley National Lab
Session chair: Lorenzo Di Tucci, Politecnico di Milano, Italy
10.00 - 10.30 Coffee break
10.30 - 12.15 Invited papers session
(4 full paper presentations)
Session chair: Zhiru Zhang, Cornell University, New York, USA
103 Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Donatella Sciuto and Marco Domenico Santambrogio: A Scalable FPGA Design for Cloud N-Body Simulation
100 Ahmet Erdem, Cristina Silvano, Thomas Boesch, Andrea Ornstein, Surinder-Pal Singh and Giuseppe Desoli: Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC
101 Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung and Wayne Luk: Hardware Compilation of Deep Neural Networks: An Overview
102 George Plastiras, Maria Terzi, Christos Kyrkou and Theocharis Theocharides: Edge Intelligence: Challenges and Opportunities of Near-Sensor Machine Applications
12.15 - 13.30 Lunch
13.30 - 14.30 Keynote: Google Pixel Visual Core: A Portable Domain-Specific Processor for Computational Photography and Machine Learning
Andrea Di Blas, Software Engineer at Google
Session chair: Marco Rabozzi, Politecnico di Milano, Italy
14.30 - 15.45 Paper session - Applications: Image Processing and Machine Learning
(3 full paper presentations)
Session chair: Lorenzo Di Tucci, Politecnico di Milano, Italy
19 Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren and Ben Jeppesen. Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control
72 Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya and Ajith Pasqual: Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutional Neural Networks
42 Yang Yue, Ying Li, Kexin Yi and Zhonghai Wu. SDACR: Synthetic Data Approach for Classification and Regression
15.45 - 16.15 Coffee break
16.15 - 17.45 Paper session - Applications: Bioinformatics
(3 full paper presentations + 1 short paper presentation)
Session chair: Giulia Guidi, Politecnico di Milano, Italy
12 Nasrin Akbari, Mehdi Modarressi, Masoud Daneshtalab and Mohammad Loni: A Customized Processing-in-Memory Architecture for Biological Sequence Alignment
55 Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen and Yi-Chang Lu: Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator
47 Davide Sampietro, Chiara Crippa, Lorenzo Di Tucci, Emanuele Del Sozzo and Marco Domenico Santambrogio: FPGA-based PairHMM Forward Algorithm for DNA Variant Calling
92 Huiren Li, Anand Ramachandran and Deming Chen. GPU Acceleration of Advanced $k$-mer Counting for Computational Genomics
18.15 - 23.00 Social Dinner: Wine tasting in Franciacorta
18.15 Meet at Politecnico di Milano at: Via Golgi 39, 20133 Milano
18.30 Departure by private bus from Politecnico di Milano to Polastri Maceler (Via Quattro Vie 1, Torbiato di Adro, Brescia)
19.30 Arrival at Polastri Maceler
19.45 Welcome aperitivo
20.00 - 23.00 Local dishes and wine from the Franciacorta tradition
July 12, 2018
09.00 - 10.00 Keynote: Design Trade-offs for Machine Learning Solutions on Reconfigurable Devices
Michaela Blott, Principal Engineer at Xilinx
Session chair: Lorenzo Di Tucci, Politecnico di Milano, Italy
10.00 - 10.30 Coffee break
10.30 - 12.15 Paper session - Architectures
(4 full paper presentations)
Session chair: Gian Domenico Licciardo, Università degli Studi di Salerno, Italy
74 Jose Raul Garcia Ordaz and Dirk Koch: A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine
7 Dimitris Theodoropoulos, Andrea Reale, Dimitris Syrivelis, Maciej Bielski, Nikolaos Alachiotis and Dionisios Pnevmatikatos: REMAP: Remote mEmory Manager for disAggregated Platforms
67 Julie Dumas, Eric Guthmuller and Frédéric Pétrot: Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach
69 Hosein Mohammadi Makrani, Hossein Sayadi, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad and Houman Homayoun: Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/O Bottleneck in Data-Intensive Workloads
12.15 - 13.00 Lunch
13.00 - 14.00 Special session on cloud computing
Session chair: Rolando Brondolin, Politecnico di Milano, Italy
Kubernetes is the new Multi Cloud
Event Driven Architectures with Apache Kafka on Heroku Platform and Salesforce Platform Events
The Great Data Lab in the Sky - Big Data on Clouds
14.00 - 15.45 Paper session - Applications: Security, Networking and Floating Point Arithmetic
(4 full paper presentations)
Session chair: Subramanian Shiva Shankar, Intel
58 Zelin Rong, Peidai Xie, Jingyuan Wang, Shenglin Xu and Yongjun Wang: Clean the Scratch Registers:A Way to Mitigate Return-Oriented Programming Attacks
39 Shiva Shankar Subramanian, Pinxing Lin, Andreas Herkersdorf and Thomas Wild: BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates
83 Tuan Nguyen, Son Bui and James Stine: Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication
53 Hugues de Lassus Saint-Geniès, Nicolas Brunie and Guillaume Revy: Meta-implementation of vectorized logarithm function in binary floating-point arithmetic
15.45 - 16.15 Coffee break
16.15 - 17.30 Paper session - Design Methodologies
(3 full paper presentations)
Session chair: Lorenzo Di Tucci, Politecnico di Milano, Italy
49 Achim Lösch and Marco Platzner: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes
51 Juan Carlos Salinas-Hilburg, Marina Zapater, José Manuel Moya and José Luis Ayala: Fast Energy Estimation Through Partial Execution of HPC Applications
16 Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig and Jürgen Teich: Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
17.30 - 18.00 Closing remarks and best paper award announcement
July 13, 2018
09-00 - 18.00 Workshop on FPGA-based Accelerated Cloud Computing @ Classroom Y.1
Presenter: Cathal McCabe - Xilinx University Program, Xilinx Ireland
09.00 - 12.00 Introduction and fundamentals:
  • Introduction to FPGA-based acceleration
  • Xilinx SDAccel development framework
  • AWS EC2 F1 platform, and use cases
12.00 - 13.00 Lunch
13.00 - 18.00 Lab session:
  • Connecting to an AWS EC2 F1 instance,
  • Using an AWS F1 instance to accelerate complex workloads,
  • Developing and optimizing AWS F1 applications with SDAccel
  • Optimizing host and FPGA code, and
  • Integrating IP into SDAccel-based code.