Google Pixel Visual Core: A Portable Domain-Specific Processor for Computational Photography and Machine Learning

Andrea Di Blas, Software Engineer at Google


Pixel Visual Core is Google's domain-specific processor for image processing, computational photography, computer vision, and machine learning applications. The main feature of Pixel Visual Core is a fully programmable Image Processing Unit (IPU). An IPU is built of a number of Stencil Processors (STP), each with a 2-dimensional array of SIMD processing elements. Between STPs, the memory system is composed of customized linebuffer memory. The overall system is optimized for stencil-type operations that are fundamental both in image processing and in neural networks. Initially targeted for mobile applications, it is powering Google's latest cellphone, Pixel 2. The first chip fully custom-designed by Google, runs HDR+ on full-resolution images with a 10x energy efficiency advantage with respect to the main application processor. In the future, the same architecture can be deployed in other contexts such as Internet of Things (IoT).

About the speaker

Andrea Di Blas Andrea Di Blas is a software engineer at Google, working on the recently released Pixel Visual Core, and also a lecturer at Stanford University where he teaches the course "Parallel Processors Beyond Multicore Processing" once a year since 2013. Before Google he was briefly a software development engineer at Amazon Fresh, and before that he was a research scientist at Oracle Labs, designing and implementing new solutions for specialized, massively-parallel machines for big data processing. Previously he was an Assistant Adjunct Professor at the School of Engineering at the University of California, Santa Cruz, where he also taught computer architecture and parallel programming. His main interests revolve around parallel programming models and parallel computing architectures, combinatorial optimization problems on graphs, consciousness, and the nature of reality. He received his M.S. in Electrical Engineering and his Ph.D. in Computer Engineering from Politecnico di Torino, Italy.