Design Trade-offs for Machine Learning Solutions on Reconfigurable Devices

Michaela Blott, Principal Engineer at Xilinx

Slides available here

Abstract

Machine learning algorithms such as Convolutional Neural Networks become increasingly popular, as their accuracy outpaces many traditional algorithms, while requiring no domain expertise and no explicit programming. However, a significant computational and memory challenge remains which limits their adoption in energy constrained compute environments. Research has shown that radical quantization of the original floating point representations of network inference parameters and processing data at extreme reduced precision is possible without significant loss in accuracy. For hardware implementations targeting currently available field programmable gate arrays (FPGAs), this provides tremendous potential to scale compute capabilities well above 100 TOPS/sec through customization of hardware circuits. Within this talk, we compare potential hardware implementations using GPUs, FPGAs and ASICs. In respect to FPGAs, we’ll take a look at some of the really interesting design trade-offs that can be achieved in the vast design space comprised of accuracy, throughput, latency and power consumption over a spectrum of implementations which leverage different architectures, numerical representations and precisions.

About the speaker

Michaela Blott is a Principal Engineer at Xilinx Research, where she is heading a team of international researchers, with over 25 years of experience in computer architecture, FPGA and board design. She is leading Xilinx’s research in regards to bringing FPGAs into new application domains, such as machine learning, hyperscale deployments, and high-speed networking, investigating system architectures with emerging memory technologies with an emphasis on building complete implementations. She graduated from the University of Kaiserslautern in Germany and worked in both research institutions (ETH and Bell Labs) as well as development organizations and was deeply involved in large scale international collaborations such as NetFPGA-10G. She is strongly involved with the international research community as technical co-chair of FPL’2018, industry advisor on numerous European research projects, organizer of a SC’2015/6/7/8 workshop and serves on the technical program committee of numerous conferences (DATE, FPGA, FPL, GLOBALSIP, Hipeac).